The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Sep. 04, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kuminori Hyodo, Kawasaki, JP;

Kenji Sakurada, Yamato, JP;

Masanobu Shirakawa, Chigasaki, JP;

Hideki Yamada, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G06F 12/02 (2006.01); G11C 16/26 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G06F 12/0246 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G06F 2212/2022 (2013.01); G11C 16/08 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11565 (2013.01);
Abstract

A memory system according to an embodiment includes a semiconductor memory and a memory controller. The semiconductor memory includes memory cells and a sequencer. Each of the memory cells stores first data when it has a first threshold voltage, and stores second data when it has a second threshold voltage. The sequencer performs a first write operation for write data. In the first write operation, the sequencer executes a program loop repeatedly and terminates the first write operation, when the verify operation for the first data has passed and the verify operation for the second data has not passed. The sequencer performs a second write operation for the write data based on a first command from the memory controller after the first write operation is terminated.


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