The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Apr. 08, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Herbert H. Hum, Portland, OR (US);

Brinda Ganesh, Hillsboro, OR (US);

James R. Vash, Littleton, MA (US);

Ganesh Kumar, Fort Collins, CO (US);

Leena K. Puthiyedath, Portland, OR (US);

Scott J. Erlanger, Boston, MA (US);

Eric J. Dehaemer, Shrewsbury, MA (US);

Adrian C. Moga, Portland, OR (US);

Michelle M. Sebot, Portland, OR (US);

Richard L. Carlson, Fort Collins, CO (US);

David Bubien, Fort Collins, CO (US);

Eric Delano, Fort Collins, CO (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0831 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01);
Abstract

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.


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