The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Jul. 31, 2019
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Chun-Cheng Liao, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66666 (2013.01); H01L 29/0657 (2013.01); H01L 29/66484 (2013.01); H01L 29/66515 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7827 (2013.01);
Abstract

The present application discloses a method for preparing a semiconductor device structure. The method includes: forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a processed area on a top portion of the substrate exposed by the annular semiconductor fin; selectively forming a spacer on a side surface of the annular semiconductor fin; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.


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