The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2020
Filed:
Jul. 26, 2018
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei, CN;
Inventors:
Xin Yun Huang, Hubei, CN;
Qi Wang, Hubei, CN;
Xiang Fu, Hubei, CN;
Zhiliang Xia, Hubei, CN;
Huang Peng Zhang, Hubei, CN;
Hua Min Cao, Hubei, CN;
Assignee:
Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei, CN;
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 21/762 (2006.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 29/739 (2006.01); H01L 29/792 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/762 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08); H01L 29/7391 (2013.01); H01L 29/7926 (2013.01);
Abstract
Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.