The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2020
Filed:
Nov. 08, 2018
Applicant:
Macronix International Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
MACRONIX INTERNATIONAL CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/28167 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract
A 3D semiconductor memory device includes a semiconductor substrate, a source line, a gate line and a plurality of memory cells connected in series. The semiconductor substrate has a protruding portion. The source line is disposed in the semiconductor substrate and partially extending below the protruding portion. The gate line is configured to surround and cover the protruding portion and electrically separated from the source line and the protruding portion. The memory cells are disposed on the semiconductor substrate and connected in series to the protruding portion at a top surface thereof.