The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Feb. 19, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Shinichi Kuwabara, Ibaraki, JP;

Yasutaka Nakashiba, Ibaraki, JP;

Tetsuya Iida, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 25/065 (2006.01); H02K 11/33 (2016.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49575 (2013.01); H01L 23/5227 (2013.01); H01L 25/50 (2013.01); H01L 28/10 (2013.01); H02K 11/33 (2016.01); H01L 2225/06531 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06582 (2013.01);
Abstract

A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.


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