The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Sep. 26, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tomas G. Akenine-Moller, Lund, SE;

Prasoonkumar Surti, Folsom, CA (US);

Altug Koker, El Dorado Hills, CA (US);

David Puffer, Tempe, AZ (US);

Jim K. Nilsson, Lund, SE;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/0875 (2016.01); G06F 12/02 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01); G06F 3/06 (2006.01); G06F 40/12 (2020.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 12/0207 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06F 3/0655 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 40/12 (2020.01); G06F 2212/1024 (2013.01); G06F 2212/302 (2013.01); G06F 2212/401 (2013.01); G06F 2212/455 (2013.01);
Abstract

Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.


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