The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Feb. 01, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alexander Gendler, Kiriat Motzkin, IL;

Larisa Novakovsky, Haifa, IL;

Ariel Szapiro, Tel Aviv, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 9/38 (2018.01); G06F 1/3206 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 9/3802 (2013.01); G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3243 (2013.01); G06F 1/3296 (2013.01); G06F 9/3881 (2013.01); Y02D 10/126 (2018.01); Y02D 10/152 (2018.01); Y02D 10/172 (2018.01); Y02D 50/20 (2018.01);
Abstract

In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.


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