The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2020

Filed:

Sep. 25, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Jerome J. Johnson, Cedar Park, TX (US);

John MacLaren, Austin, TX (US);

Sreenivasan Kandagatla, Austin, TX (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05B 19/045 (2006.01); G06F 12/126 (2016.01); G06F 9/4401 (2018.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G05B 19/045 (2013.01); G06F 9/4403 (2013.01); G06F 11/2284 (2013.01); G06F 12/126 (2013.01);
Abstract

A system and method are provided for memory control, having selectively distributed power-on processing. A memory controller executes responsive to a master control operation to actuate a plurality of operational tasks on a memory device. The memory controller includes a first power-on block executable to actuate one or both of initialization and training operations corresponding to the memory device. A PHY portion coupled to the memory controller portion executes to adaptively configure control, address, and data signals for physically compatible passage between the controller portion and memory device. The PHY portion includes a second power-on block executable to actuate one or both of an initialization operation and a training operation corresponding to the memory device. The PHY portion is configured according to the initialization and training operations, wherein each of the initialization and training operations are selectively actuated responsive to one of the power-on blocks.


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