The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jun. 12, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Bin Zhang, Suzhou, CN;

Jianluo Chen, Suzhou, CN;

Yan Huang, Suzhou, CN;

Hongyan Yao, Suzhou, CN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/1252 (2006.01); G06F 1/06 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); G06F 1/06 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01);
Abstract

A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.


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