The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jun. 11, 2018
Applicant:

Nantero, Inc., Woburn, MA (US);

Inventor:

Claude L. Bertin, Venice, FL (US);

Assignee:

Nantero, Inc., Woburn, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/28 (2006.01); B82Y 10/00 (2011.01); H01L 51/00 (2006.01); H03K 19/20 (2006.01); G06F 30/30 (2020.01); H01L 21/02 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 51/10 (2006.01); H01L 51/05 (2006.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 27/283 (2013.01); B82Y 10/00 (2013.01); G06F 30/30 (2020.01); H01L 21/02376 (2013.01); H01L 29/16 (2013.01); H01L 29/78 (2013.01); H01L 51/0048 (2013.01); H01L 51/105 (2013.01); H03K 19/20 (2013.01); B82Y 40/00 (2013.01); H01L 51/0558 (2013.01); H01L 51/0566 (2013.01); Y10S 977/742 (2013.01);
Abstract

Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.


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