The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Dec. 04, 2018
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Yuri Tkachev, Sunnyvale, CA (US);

Alexander Kotov, San Jose, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11521 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 16/0408 (2013.01); H01L 29/7885 (2013.01);
Abstract

A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.


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