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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10714482 B1

PDFFull Text
Date of Patent:
Jul. 14, 2020

Filed:

Mar. 10, 2020

Method of fabricating dynamic random access memory

Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Kazuaki Takesako, Kanagawa, JP;

Kazutaka Manabe, Kanagawa, JP;

Assignee:

Winbond Electronics Corp., Taichung, TW;

Attorney:

JCIPRNET

Primary Examiner:

Nicholas J Tobergte

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/108 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 27/10826 (2013.01); H01L 27/10876 (2013.01); H01L 27/10879 (2013.01); H01L 27/10891 (2013.01); H01L 27/1211 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7856 (2013.01);
Abstract

A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes forming a gate trench in a substrate. An isolation structure is formed in the substrate and defines a plurality of active regions arranged in a column in a first direction. A buried word line structure is formed to fill the gate trench and extend along the first direction and across the plurality of active regions and the isolation structure. A plurality of first fin structures is formed in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure. A dielectric layer is formed on the substrate to fill the gate trench and cover the buried word line structure.

Find Patent Forward Citations

Takesako, Kazuaki. (2020). Method of fabricating dynamic random access memory (U.S. Patent No. 10714482). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10714482

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