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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10714377 B1

PDFFull Text
Date of Patent:
Jul. 14, 2020

Filed:

Sep. 05, 2018

Semiconductor device and semiconductor wafer including a porous layer and method of manufacturing

Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Ingo Muri, Villach, AT;

Bernhard Goller, Villach, AT;

Iris Moder, Villach, AT;

Hans-Joachim Schulze, Taufkirchen, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:

Murphy, Bilak & Homiller, PLLC

Primary Examiner:

Hsien Ming Lee

Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/861 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/32 (2006.01); H01L 21/02 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76245 (2013.01); H01L 21/02238 (2013.01); H01L 21/02494 (2013.01); H01L 21/02532 (2013.01); H01L 21/306 (2013.01); H01L 21/30625 (2013.01); H01L 22/26 (2013.01); H01L 23/562 (2013.01); H01L 29/0692 (2013.01); H01L 29/0834 (2013.01); H01L 29/32 (2013.01); H01L 29/66128 (2013.01); H01L 29/66333 (2013.01); H01L 29/66348 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 29/8611 (2013.01); H01L 21/02255 (2013.01); H01L 21/02258 (2013.01); H01L 21/02513 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0634 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/4236 (2013.01); H01L 29/6606 (2013.01); H01L 29/7391 (2013.01); H01L 29/7394 (2013.01); H01L 29/7395 (2013.01); H01L 29/7811 (2013.01); H01L 29/7812 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.

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