The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jan. 15, 2019
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wu-Chang Chang, Hsinchu County, TW;

Cheng-Te Yang, Hsinchu County, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); H03K 5/134 (2014.01); G11C 5/14 (2006.01); H02M 3/07 (2006.01); H03K 17/687 (2006.01); G11C 7/22 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 7/14 (2006.01); G11C 16/28 (2006.01); G11C 29/00 (2006.01); H03K 3/012 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 23/525 (2006.01); H01L 27/112 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); G11C 11/419 (2006.01); G11C 13/00 (2006.01); H03K 5/00 (2006.01); H03K 5/159 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 5/145 (2013.01); G11C 5/147 (2013.01); G11C 7/062 (2013.01); G11C 7/12 (2013.01); G11C 7/14 (2013.01); G11C 7/18 (2013.01); G11C 7/22 (2013.01); G11C 16/28 (2013.01); G11C 17/165 (2013.01); G11C 17/18 (2013.01); G11C 29/78 (2013.01); H01L 23/5252 (2013.01); H01L 27/11206 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/42376 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01); H02M 3/07 (2013.01); H03K 3/012 (2013.01); H03K 5/134 (2014.07); H03K 17/687 (2013.01); G11C 7/06 (2013.01); G11C 11/419 (2013.01); G11C 2013/0042 (2013.01); G11C 2207/002 (2013.01); G11C 2207/005 (2013.01); G11C 2211/4013 (2013.01); H02M 2003/075 (2013.01); H03K 5/159 (2013.01); H03K 2005/00195 (2013.01);
Abstract

A charge pump circuit includes a voltage input port, a voltage output port, a plurality of charge pump units cascaded between the voltage input port and the voltage output port, a clock signal source, and N clock delay elements. The clock signal source generates a main clock signal and the N clock delay elements generate clock signals received by the charge pump units by delaying the main clock signal. The main clock signal received by the first charge pump unit has a rising edge leading a rising edge of the last clock signal received by the last charge pump unit, and a falling edge lagging the rising edge of the last clock signal. Each of the charge pump units includes two sets of inverters with delay elements for generating two complementary clock signals.


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