The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jun. 30, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rahul Bera, Bangalore, IN;

Anant Vithal Nori, Bangalore, IN;

Sreenivas Subramoney, Bangalore, IN;

Hong Wang, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 12/0875 (2016.01); G06F 12/0862 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3802 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/084 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6022 (2013.01); G06F 2212/6024 (2013.01);
Abstract

An apparatus and method for adaptive spatial accelerated prefetching. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and process data; a Level 2 (L2) cache to store at least a portion of the data; and a prefetcher to prefetch data from a memory subsystem to the L2 cache in anticipation of the data being needed by the execution unit to execute one or more of the instructions, the prefetcher comprising a buffer to store one or more prefetched memory pages or portions thereof, and signature data indicating detected patterns of access to the one or more prefetched memory pages; wherein the prefetcher is to prefetch one or more cache lines based on the signature data.


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