The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Jun. 06, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mandeep Singh, Union City, CA (US);

Mohammad Abdallah, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/34 (2018.01); G06F 9/38 (2018.01); G06F 12/0888 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/34 (2013.01); G06F 9/3834 (2013.01); G06F 12/0888 (2013.01); G06F 13/1642 (2013.01); G06F 2212/6046 (2013.01);
Abstract

Fast unaligned memory access. hi accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.


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