The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Oct. 18, 2018
Applicant:

Philips Photonics Gmbh, Ulm, DE;

Inventors:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/028 (2006.01); H01L 23/544 (2006.01); H01S 5/42 (2006.01); H01S 5/042 (2006.01); H01S 5/183 (2006.01); H01L 31/16 (2006.01); H01S 5/22 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01S 5/028 (2013.01); H01L 23/544 (2013.01); H01L 31/16 (2013.01); H01S 5/042 (2013.01); H01S 5/18327 (2013.01); H01S 5/22 (2013.01); H01S 5/423 (2013.01); H01L 22/30 (2013.01); H01L 2223/5448 (2013.01); H01L 2223/54413 (2013.01); H01L 2223/54433 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The invention describes a laser device comprising between two and six mesas () provided on one semiconductor chip (), wherein the mesas () are electrically connected in parallel such that the mesas () are adapted to emit laser light if a defined threshold voltage is provided to the mesas (). Two to six mesas () with reduced active diameter in comparison to a laser device with one mesa improve the yield and performance despite of the fact that two to six mesas need more area on the semiconductor chip thus increasing the total size of the semiconductor chip (). The invention further describes a method of marking semiconductor chips (). A functional layer of the semiconductor chip () is provided and structured in a way that a single semiconductor chip () can be uniquely identified by means of optical detection of the structured functional layer. The structured layer enables identification of small semiconductor chips () with a size below 200 μm×200 μm.


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