The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Sep. 16, 2019
Applicant:

Longitude Flash Memory Solutions Ltd., Dublin, IE;

Inventors:

Sungkwon Lee, Saratoga, CA (US);

Venkatraman Prabhakar, Pleasanton, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); H01L 27/11582 (2017.01); H01L 49/02 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/11582 (2013.01); H01L 28/00 (2013.01); G11C 16/0433 (2013.01);
Abstract

A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.


Find Patent Forward Citations

Loading…