The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Apr. 03, 2019
Applicant:
Synopsis, Inc., Mountain View, CA (US);
Inventors:
Harold Pilo, Underhill, VT (US);
John Edward Barth, Jr., Williston, VT (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/417 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01);
Abstract
An integrated level-shifter and memory clock is disclosed that minimizes delay of voltage level-shifting from an external clock on a first logic supply voltage to an internal clock on a higher array supply voltage that is pulse-width independent of the external clock used to generate the internal clock. The generation of the internal clock on the higher array supply voltages is accomplished in two stages of logic. An array-tracking timing delay circuit mimics access delay to generate a MRST_P to reset the internal clock on the higher array supply voltage.