The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Feb. 25, 2019
Applicant:
Rambus Inc., Sunnyvale, CA (US);
Inventors:
Frederick A. Ware, Los Altos Hills, CA (US);
Ely K. Tsern, Los Altos, CA (US);
Richard E. Perego, Thornton, CO (US);
Craig E. Hampel, Los Altos, CA (US);
Assignee:
Rambus Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/4076 (2006.01); G11C 7/10 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 5/06 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 8/18 (2006.01); G11C 7/22 (2006.01); G06F 1/10 (2006.01); G11C 11/409 (2006.01); G11C 11/4096 (2006.01); G06F 1/06 (2006.01); G06F 1/12 (2006.01); G06F 3/06 (2006.01); G11C 7/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/06 (2013.01); G06F 1/105 (2013.01); G06F 1/12 (2013.01); G06F 3/0604 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G06F 13/1684 (2013.01); G06F 13/1689 (2013.01); G06F 13/1694 (2013.01); G06F 13/4086 (2013.01); G11C 5/063 (2013.01); G11C 7/1051 (2013.01); G11C 7/1072 (2013.01); G11C 7/1078 (2013.01); G11C 7/22 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 11/409 (2013.01); G11C 11/4096 (2013.01); G11C 29/02 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 29/50008 (2013.01); G11C 29/50012 (2013.01); G11C 7/04 (2013.01);
Abstract
A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.