The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

May. 14, 2018
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Jackey Z. Yan, Sunnyvale, CA (US);

Cindy Zhang, Pudong District, CN;

Pinhong Chen, Saratoga, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/392 (2020.01); H04W 16/32 (2009.01); G06F 3/0484 (2013.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 3/04842 (2013.01); H04W 16/32 (2013.01);
Abstract

Aspects of the present disclosure address systems, methods, and an improved graphical user interface (GUI) for providing interactive macro-cell placement for integrated circuit (IC) design. The method includes causing display of a GUI that includes a display of an IC floor plan comprising multiple macro-cells, The method further includes receiving a user selection of two or more macro-cells from the IC floor plan, and updating the GUI to display layout options for the two or more macro-cells in conjunction with the display of the IC floor plan. Each layout option specifies an arrangement of the two or more macro-cells. In response to a user selection of a layout option, the display of the IC floor plan is updated by modifying a placement of the two or more macro-cells in accordance with the selected layout option.


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