The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Mar. 30, 2018
Synopsys, Inc., Mountain View, CA (US);
David L. Allen, Fremont, CA (US);
Kaushik De, Pleasanton, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A method and EDA software tool for analyzing and verifying that a multi-level power managed system description (IC design) is free of power-state combination conflicts by way of identifying and reconciling voltage level and power-state combination conflicts caused by reused blocks (IP cores). The reconciliation process involves generating Power-State Tables (PSTs) associated with each hierarchical circuit level (e.g., top/system level and lower/block levels) of the IC design using both initial power supply voltage values and reconciled/revised voltage values, which are determined by the main driver voltage levels of each power supply. Initial supply relationships generated using the initial PSTs are then compared with final supply relationships generated using the reconciled PSTs, whereby conflicts are identified when one or more initial supply relationship fails to match a final supply relationship, or when one or more final supply relationship fails to match an initial supply relationship.