The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
May. 04, 2017
Nvidia Corporation, Santa Clara, CA (US);
Xiaogang Qiu, San Jose, CA (US);
Ronny Krashinsky, San Francisco, CA (US);
Steven Heinrich, Madison, AL (US);
Shirish Gadre, Fremont, CA (US);
John Edmondson, Arlington, MA (US);
Jack Choquette, Palo Alto, CA (US);
Mark Gebhart, Round Rock, TX (US);
Ramesh Jandhyala, Austin, TX (US);
Poornachandra Rao, Cedar Park, TX (US);
Omkar Paranjape, Austin, TX (US);
Michael Siu, Santa Clara, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.