The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Nov. 27, 2018
Marvell International Ltd., Hamilton, BM;
Ranjan B. Lokappa, Winooski, VT (US);
Igor Arsovski, Williston, VT (US);
MARVELL INTERNATIONAL LTD., Hamilton, BM;
Abstract
Disclosed is a parallel prefix adder structure with a carry bit generation circuit that generates primary carry bits for only some bit pairs and a sum circuit with ripple carry adders that use these primary carry bits to generate secondary carry bits and sum bits for a final sum. The carry bit generation circuit has different sections, which process different sequential sets of bit pairs and which have different sparsity configurations. As a result, generation of the primary carry bits is non-uniform. That is, in the different sections the primary carry bits are generated at different carry bit-to-bit pair ratios (e.g., the carry bit-to-bit pair ratios for the different sections can be 1:2, 1:4, and 1:2, respectively). For optimal performance, the specific bit pairs for which these primary carry bits are generated varies depending upon whether the maximum operand size is an odd number of bits or an even number.