The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Nov. 13, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Alexander Gendler, Kiriat Motzkin, IL;

Kosta Luria, Pardesiya, IL;

Arye Albahari, Kiriat Yam, IL;

Ohad Nachshon, Haifa, IL;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/3206 (2019.01); G06F 1/3296 (2019.01); G06F 1/324 (2019.01); G01R 19/165 (2006.01); G06F 1/06 (2006.01); G06F 1/26 (2006.01); G01R 1/20 (2006.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G01R 19/16528 (2013.01); G01R 19/16533 (2013.01); G06F 1/06 (2013.01); G06F 1/26 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3296 (2013.01); G01R 1/203 (2013.01); G01R 19/0092 (2013.01);
Abstract

A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.


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