The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2020
Filed:
Dec. 14, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G04F 10/00 (2006.01); H03L 7/089 (2006.01); H03L 7/099 (2006.01); H03L 7/18 (2006.01); H03L 7/093 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0893 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01); H03L 7/18 (2013.01); G04F 10/005 (2013.01);
Abstract
Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.