The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Dec. 27, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ravindar Attineni, Singapore, SG;

Sachin Mathur, Bangalore, IN;

Jiaxiang Shi, Singapore, SG;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/087 (2006.01); H03L 7/093 (2006.01); H03L 7/081 (2006.01); G01R 31/319 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
H03L 7/081 (2013.01); G01R 31/31922 (2013.01); G06F 1/12 (2013.01);
Abstract

A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift.


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