The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Oct. 28, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kuang-Hsiu Chen, Tainan, TW;

Sung-Yuan Tsai, Yunlin County, TW;

Chi-Hsuan Tang, Kaohsiung, TW;

Kai-Hsiang Wang, Taichung, TW;

Chao-Nan Chen, Tainan, TW;

Shi-You Liu, Kaohsiung, TW;

Chun-Wei Yu, Tainan, TW;

Yu-Ren Wang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/26506 (2013.01); H01L 21/26586 (2013.01); H01L 29/165 (2013.01); H01L 29/6653 (2013.01); H01L 29/6659 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01);
Abstract

A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.


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