The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Dec. 26, 2018
Applicant:

Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai, CN;

Inventor:

Xianzhou Liu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/28 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 21/3213 (2006.01); H01L 27/11521 (2017.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); G11C 16/0408 (2013.01); G11C 16/0458 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 21/32139 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line structure between the first memory region and the second memory region. The word-line structure includes, stacked on the surface of the semiconductor substrate sequentially from bottom to top, a word-line oxide layer, a read gate, a dielectric oxide layer and an erase gate. The read and erase gates can each function as a word line of the split-gate flash memory for enabling a read or erase operation. During the erase operation, a voltage applied on the erase gate has an insignificant impact on the underlying semiconductor substrate, which is helpful in reducing channel leakage in the semiconductor substrate.


Find Patent Forward Citations

Loading…