The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Nov. 16, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

June-hong Park, Seongnam-si, KR;

Bong-soon Lim, Seoul, KR;

Il-han Park, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 27/06 (2006.01); H01L 23/535 (2006.01); H01L 21/8234 (2006.01); G11C 16/04 (2006.01); H01L 27/11582 (2017.01); H01L 27/11531 (2017.01); H01L 27/11573 (2017.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 16/0483 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 23/535 (2013.01); H01L 27/0688 (2013.01); H01L 27/11286 (2013.01); H01L 27/11531 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract

A nonvolatile memory device and a method of manufacturing the device, the device including a first semiconductor layer, the first semiconductor layer including an upper substrate, and a memory cell array, the memory cell array including a plurality of gate conductive layers stacked on the upper substrate and a plurality of pillars passing through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the upper substrate; and a second semiconductor layer under the first semiconductor layer, the second semiconductor layer including a lower substrate, at least one contact plug between the lower substrate and the upper substrate, and a common source line driver on the lower substrate and configured to output a common source voltage for the plurality of pillars through the at least one contact plug.


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