The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Aug. 07, 2018
Applicant:

Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);

Inventors:

Dale A Rickard, Manassas, VA (US);

Jason F Ross, Haymarket, VA (US);

John T Matta, Nokesville, VA (US);

Richard J Ferguson, Bealeton, VA (US);

Alan F Dennis, Chantilly, VA (US);

Joseph R Marshall, Jr., Manassas, VA (US);

Daniel L Stanley, Warrenton, VA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 27/112 (2006.01); H01L 23/42 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 27/11206 (2013.01); H01L 23/367 (2013.01); H01L 23/42 (2013.01); H01L 2224/16225 (2013.01);
Abstract

An MCM-HIC device flexibly adds enhanced features to a VLSI 'core' IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one 'chiplet' that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or 'mixed' chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.


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