The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Jan. 10, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Wen Liu, South Burlington, VT (US);

Sebastian T. Ventrone, South Burlington, VT (US);

Adam C. Smith, Essex Junction, VT (US);

Janice M. Adams, Jericho, VT (US);

Nazmul Habib, Colchester, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/78 (2006.01); H01L 21/66 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 22/32 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/5448 (2013.01); H01L 2223/54433 (2013.01);
Abstract

Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.


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