The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2020
Filed:
Jul. 24, 2017
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Stephen Alan Fanelli, San Marcos, CA (US);
Richard Hammond, Gwent, GB;
Assignee:
Qualcomm Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/683 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/78 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 21/0245 (2013.01); H01L 21/02513 (2013.01); H01L 21/02532 (2013.01); H01L 21/02667 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01);
Abstract
A method of dicing a semiconductor wafer may include forming a porous silicon layer along an outline of dies singulated from the semiconductor wafer. The method may include sealing an active surface of the semiconductor wafer, including the porous silicon layer. The method may further include back grinding a rear surface of the semiconductor wafer to expose the porous silicon layer along the outline of the dies. The method also includes etching the semiconductor wafer to release the dies.