The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Aug. 29, 2018
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Wei-Chang Liu, Singapore, SG;

Zhen Chen, Singapore, SG;

Shen-De Wang, Hsinchu County, TW;

Wang Xiang, Singapore, SG;

Wei Ta, Singapore, SG;

Ling-Gang Fang, Singapore, SG;

Shang Xue, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/8239 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823456 (2013.01); H01L 21/82345 (2013.01); H01L 21/82385 (2013.01); H01L 21/823443 (2013.01); H01L 21/823468 (2013.01); H01L 21/823835 (2013.01); H01L 21/823864 (2013.01); H01L 27/088 (2013.01); H01L 27/0922 (2013.01); H01L 29/42376 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66484 (2013.01); H01L 29/7831 (2013.01); H01L 21/8239 (2013.01); H01L 29/4234 (2013.01); H01L 29/42356 (2013.01);
Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.


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