The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Oct. 04, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Cornelius B. Peethala, Slingerlands, NY (US);

Raghuveer R. Patlolla, Guilderland, NY (US);

Chih-Chao Yang, Glenmont, NY (US);

Roger A. Quon, Rhinebeck, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7684 (2013.01); H01L 21/31144 (2013.01); H01L 21/32134 (2013.01); H01L 21/7685 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/53238 (2013.01); H01L 23/53257 (2013.01); H01L 21/3212 (2013.01);
Abstract

A method for back end of line (BEOL) integration for one or more interconnects includes forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric, forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers to remove portions of the diffusion barrier layer along the interlevel dielectric.


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