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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10699914 B1

PDFFull Text
Date of Patent:
Jun. 30, 2020

Filed:

Aug. 22, 2018

On-chip heating and self-annealing in finfets with anti-punch-through implants

Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Hiu Yung Wong, Cupertino, CA (US);

Victor Moroz, Saratoga, CA (US);

Qiang Lu, Foster City, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:

Haynes Beffel & Wolfeld LLP

Andrew L. Dunlap

Warren S. Wolfeld

Primary Examiner:

Feifei Yeung Lopez

Int. Cl.
CPC ...
H01L 21/477 (2006.01); H01L 21/84 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
H01L 21/477 (2013.01); H01L 21/845 (2013.01); H01L 27/0886 (2013.01); H01L 27/092 (2013.01); H01L 29/1083 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); B82Y 10/00 (2013.01);
Abstract

The independent claims of this patent signify a concise description of the embodiments. Disclosed is technology for reducing transistor degradations by annealing through heat generated by anti-punch-through implants of the transistors. A first and second electrically conductive pillars are disposed on top a well hosting the transistors. A voltage applied across the first and second pillars enable the anti-punch-through implants to generate heat for the annealing process.

Find Patent Forward Citations

Wong, Hiu. (2020). On-chip heating and self-annealing in finfets with anti-punch-through implants (U.S. Patent No. 10699914). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10699914

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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