The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 30, 2020
Filed:
May. 14, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Krishna K. Parat, Palo Alto, CA (US);
Pranav Kalavade, San Jose, CA (US);
Koichi Kawai, Kanagawa, JP;
Akira Goda, Boise, ID (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/16 (2006.01); G11C 8/12 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 8/12 (2013.01); G11C 16/04 (2013.01); G11C 16/3409 (2013.01); G11C 16/3445 (2013.01);
Abstract
Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify.