The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Sep. 27, 2018
Applicant:

Crossbar, Inc., Santa Clara, CA (US);

Inventors:

Mehdi Asnaashari, Danville, CA (US);

Hagop Nazarian, San Jose, CA (US);

Christophe Sucur, San Jose, CA (US);

Sylvain Dubois, San Francisco, CA (US);

Assignee:

CROSSBAR, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 7/18 (2006.01); G11C 8/12 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 8/14 (2006.01); G06F 17/16 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G06F 17/16 (2013.01); G11C 7/18 (2013.01); G11C 8/12 (2013.01); G11C 8/14 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0097 (2013.01); G11C 2029/0411 (2013.01); G11C 2213/71 (2013.01); G11C 2213/75 (2013.01); G11C 2213/79 (2013.01);
Abstract

Provided herein is a computing memory architecture. The non-volatile memory architecture can comprise a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines, a first data interface for receiving data from an external device and for outputting data to the external device, and a second data interface for outputting data to the external device. The non-volatile memory architecture can also comprise programmable processing elements connected to respective sets of the multiple sets of bitlines of the resistive random access memory array, and connected to the data interface. The programmable processing elements are configured to receive stored data from the resistive random access memory array via the respective sets of bitlines or to receive external data from the external device via the data interface, and execute a logical or mathematical algorithm on the external data or the stored data and generate processed data.


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