The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Jan. 25, 2019
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Huan Yun Zhang, Shanghai, CN;

Jian Wu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 21/28 (2006.01); H01L 21/266 (2006.01); H01L 21/306 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/266 (2013.01); H01L 21/28194 (2013.01); H01L 21/30604 (2013.01); H01L 29/0847 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

Semiconductor device and fabrication method are provided. The fabrication method includes: providing a base substrate having a first gate dielectric film thereon; forming a first gate electrode layer on a portion of the first gate dielectric film; forming an offset sidewall film on the first gate dielectric film and covering sidewalls of the first gate electrode layer; forming lightly doped regions in the base substrate on sides of the first gate electrode layer; removing the offset sidewall film and a portion of the first gate dielectric film to form a first dielectric layer under the first gate electrode layer; forming sidewall spacers; forming source/drain doped regions on sides of the first gate electrode layer; forming a dielectric layer over the source/drain doped regions and the base substrate; and forming a gate opening in the dielectric layer by removing the first gate electrode layer and the first gate dielectric layer.


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