Electrostatic discharge (esd) robust transistors and related methods

Abstract

An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses. In implementations the transistor includes a silicon controlled rectifier (SCR) junction field effect transistor (SCR JFET) or a laterally diffused metal-oxide semiconductor (SCR LDMOS).