The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Mar. 28, 2019
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Ting-You Lin, Hsinchu, TW;

Chi-Li Tu, Cyonglin Township, Hsinchu County, TW;

Shin-Cheng Lin, Tainan, TW;

Yu-Hao Ho, Keelung, TW;

Cheng-Tsung Wu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/10 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/055 (2006.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); H01L 23/055 (2013.01); H01L 23/5226 (2013.01); H01L 23/562 (2013.01);
Abstract

A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.


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