The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

May. 20, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yongjun Jeff Hu, Boise, ID (US);

Tsz W. Chan, Boise, ID (US);

Christopher W. Petz, Boise, ID (US);

Everett Allen McTeer, Eagle, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0004 (2013.01); H01L 27/2409 (2013.01); H01L 27/2463 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/141 (2013.01); H01L 45/142 (2013.01); H01L 45/143 (2013.01); H01L 45/144 (2013.01); H01L 45/145 (2013.01); H01L 45/148 (2013.01); H01L 45/1625 (2013.01); H01L 45/1675 (2013.01); G11C 2213/35 (2013.01); G11C 2213/52 (2013.01); G11C 2213/71 (2013.01); H01L 27/2481 (2013.01);
Abstract

Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.


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