The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2020
Filed:
Dec. 12, 2017
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventor:
Jongtae Kwak, Boise, ID (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 11/22 (2006.01); G11C 11/406 (2006.01); G11C 29/52 (2006.01); G11C 11/4076 (2006.01); G11C 11/4099 (2006.01); G11C 7/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/106 (2013.01); G11C 11/221 (2013.01); G11C 11/406 (2013.01); G11C 11/4076 (2013.01); G11C 11/4099 (2013.01); G11C 29/52 (2013.01); G11C 7/1006 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2211/4062 (2013.01);
Abstract
Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.