The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Nov. 27, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Chao Zheng, Shanghai, CN;

Wei Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/00 (2006.01); B81C 1/00 (2006.01); B81B 3/00 (2006.01);
U.S. Cl.
CPC ...
B81B 3/0086 (2013.01); B81B 7/0006 (2013.01); B81C 1/00357 (2013.01); B81C 1/00523 (2013.01); B81C 1/00698 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/04 (2013.01); B81B 2207/07 (2013.01);
Abstract

A semiconductor device includes a bottom substrate, a sacrificial layer on the bottom substrate and including a first opening exposing a first portion of the bottom substrate and a second opening exposing a second portion of the bottom substrate, a top substrate on the sacrificial layer and on the second opening forming a cavity, a first metal layer on the top substrate and/or on the exposed first portion of the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer defining one or more pads. The pad includes a stack-layered structure of a first metal layer on the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer. The thus formed structure reduces the pad contact resistance.


Find Patent Forward Citations

Zheng, Chao. (2020). Low contact resistance semiconductor structure and method for manufacturing the same (U.S. Patent No. 10689246). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10689246

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…