The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Jun. 26, 2017
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Bee Yee Ng, Bayan Lepas, MY;

Hee Kong Phoon, Bagan Serai, MY;

Teik Hong Ooi, Bagan Serai, MY;

Guan Hoe Oh, Alo Setar, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17728 (2020.01); H03K 19/1776 (2020.01); H03K 19/00 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17728 (2013.01); H03K 19/0016 (2013.01); H03K 19/1737 (2013.01); H03K 19/1776 (2013.01);
Abstract

A programmable integrated circuit with lookup table circuitry is provided. The lookup table (LUT) circuitry may be formed using multiplexers. A multiplexer in the lookup table circuitry may be implemented using only tristate inverting circuits. Each tristate inverting circuit may include a first set of n-channel and p-channel transistors that receive a static control bit from a memory element and a second set of n-channel and p-channel transistors that receive true and complementary versions of a user signal. The first and second sets of transistors may be coupled in series between a positive power supply terminal and a ground power supply terminal. A LUT multiplexer implemented in this way need not include separate transmission gates at the output of each tristate inverting circuit and may exhibit minimal subthreshold leakage.


Find Patent Forward Citations

Loading…