The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Mar. 02, 2017
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Yu-Hung Liao, Toufen, TW;

Samuel C. Pan, Hsinchu, TW;

Sheng-Ting Fan, Taipei, TW;

Min-Hung Lee, New Taipei, TW;

Chee-Wee Liu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11585 (2017.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/1159 (2017.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); H01L 27/1159 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.


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