The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Mar. 11, 2019
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Shan Gao, Malta, NY (US);

Boo Yang Jung, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/00 (2006.01); H01L 27/22 (2006.01); H01L 25/065 (2006.01); H05K 1/02 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); H05K 1/05 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 3/32 (2006.01); H05K 3/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/222 (2013.01); H01L 23/552 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H05K 1/0225 (2013.01); H05K 1/05 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 3/32 (2013.01); H05K 3/4038 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H05K 2201/0715 (2013.01); H05K 2201/0723 (2013.01); H05K 2201/10159 (2013.01);
Abstract

Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.


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