The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Feb. 21, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Hiroshi Kanno, Yokkaichi, JP;

Tomofumi Zushi, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/11556 (2013.01); H01L 21/31116 (2013.01);
Abstract

A semiconductor memory device according to an embodiment includes a base portion, a laminated body, a second conductive layer, and a columnar body. The columnar body includes a semiconductor body and a charge storage film. The semiconductor body includes a first region and a second region. The first region extends from a connection portion between the semiconductor body and the first semiconductor portion to the inside of the second conductive layer. The first region includes a first material. The second region is positioned closer to the laminated body than the first region is and is configured such that at least a portion is present within the second conductive layer. The second region does not include the first material or has a concentration of the first material which is lower than that in the first region. A first outer circumferential length of the semiconductor body within the second conductive layer is larger than a second outer circumferential length of the semiconductor body on a first surface which is an interface between the second conductive layer and the laminated body.


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