The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Nov. 07, 2017
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Xi Lin, Shanghai, CN;

Yi Hua Shen, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10852 (2013.01); H01L 21/768 (2013.01); H01L 27/10805 (2013.01); H01L 27/10808 (2013.01); H01L 27/10826 (2013.01); H01L 27/10879 (2013.01); H01L 27/10885 (2013.01); H01L 27/2436 (2013.01); H01L 28/40 (2013.01); H01L 28/82 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/065 (2013.01); H01L 45/085 (2013.01); H01L 45/124 (2013.01); H01L 45/1253 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/16 (2013.01); H01L 45/1683 (2013.01);
Abstract

Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming doped source/drain regions in the base substrate at two sides of the gate structure, respectively; forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions; forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and forming a memory structure in the first opening and on the one of doped source/drain regions.


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